The present invention relates generally to non-volatile memory devices and, more particularly, to methods and systems of controlling the boosted voltage level that is applied to wordlines in flash electrically erasable programmable read-only memory (EEPROM) during read operations.
Flash memories are popular memory storage devices because they store information in the absence of continuous power and are capable of being constructed in a very compact form. Flash memory is typically constructed by fabricating a plurality of floating-gate transistors in a silicon substrate. A floating-gate transistor is capable of storing electrical charge on a separate gate electrode, known as a floating gate, that is separated by a thin dielectric layer from a control-gate electrode. Generally speaking, data is stored in a non-volatile memory device by the storage of an electrical charge in the floating gate.
In a flash EEPROM device, electrons are transferred to the floating-gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating-gate electrode and an underlying substrate. Typically, the electron transfer is carried out by channel hot electron (xe2x80x9cCHExe2x80x9d) injection or Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage is coupled to the floating-gate electrode by a control-gate electrode. The control-gate electrode is capacitively coupled to the floating-gate electrode, such that a voltage applied to the control-gate electrode is coupled to the floating-gate electrode. In one type of device, the control-gate electrode is a polycrystalline silicon-gate electrode overlying the floating-gate electrode and separated therefrom by the thin dielectric layer. In another type of device, the floating-gate electrode is a doped region in the semiconductor substrate.
Flash memory is formed by rows and columns of flash transistors, with each transistor being referred to as a cell that includes a control gate, a drain and a source. A wordline decoder provides operational voltages to rows of transistors in each sector of the memory device and is typically connected with the control gate of each transistor in a sector. A bitline decoder provides operational voltages to columns of transistors and is typically connected to the drains of the transistors in each column. Generally, the sources of the transistors are coupled to a common sourceline and are controlled by a sourceline controller.
A cell is typically programmed by applying a predetermined voltage to the control gate, a second predetermined voltage to the drain, and grounding the source. This causes channel hot electrons to be injected from the drain depletion region into the floating gate. A cell can be erased several ways in a flash memory device. In one arrangement, a cell is erased by applying a predetermined voltage to the source, grounding the control gate and allowing the drain to float. This causes the electrons that were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel-oxide layer to the source.
Cells are typically read during a read operation by applying a predetermined threshold voltage to the control gate via a wordline, a second predetermined voltage to the bitline, to which the drain is connected, grounding the source, and then sensing the bitline current. If the cell is programmed and a threshold voltage is relatively high, the bitline current will be zero or relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low, the predetermined voltage on the control gate will enhance the channel and the bitline current will be relatively high.
Known problems occur during the read operation when a voltage applied to the wordline is not within a predetermined threshold voltage range. If the voltage applied to the wordline decoder is too high, the cells on that wordline can be physically damaged or there can be a disturbance of the threshold voltage of the cells. In addition, applying a voltage that is too high can also cause data retention failure within the cells. High voltages on the wordline can also affect the endurance of the cells on a given wordline. If the wordline voltage is too low, insufficient bitline current may be developed to properly read a cell on the wordline.
Presently known methods of supplying voltage to the wordlines during a read operation use a supply voltage (Vcc) that is typically boosted to a higher operational value during the read operation. As flash memory technology has advanced and smaller technologies have been developed (0.25 micron cell sizes), the voltage value of the supply voltage (Vcc) has been decreased from approximately 5 V to 3 V. Because of these advances, the acceptable range of voltage allowed to be supplied to the wordlines during a read operation has been reduced.
During fabrication of flash memory, even slight variations experienced during the fabrication process can cause the boosted voltage that the wordlines need to be supplied during a read operation to vary from chip to chip. The resulting wider variation of the boosted wordline voltage can be tolerated by the core cell for 0.35 micron process. However, for 0.25 micron process, where the gate-coupling of the core cells was increased, gate disturb is more likely requiring tighter control of the wordline threshold voltage level that is applied to the gates of the core cells during a read operation.
To that end, due to the further miniaturization of microchips, a need exists for methods and systems of providing tighter control of the boosted voltage level that is supplied to the wordlines during a read operation. MINIMIZE PROCESS VARIATION OF BOOSTED WORDLINE VOLTAGE
The present invention discloses a method of generating and tightly controlling a boosted wordline voltage that is used during read operations in a flash memory. In the preferred embodiment, a gate voltage is generated within a wordline voltage booster circuit that is clamped with an adjustable clamp circuit, which is electrically connected to the wordline voltage booster circuit. The adjustable clamp circuit is designed to take effect at a predetermined voltage level, which indirectly controls the voltage level of the boosted wordline voltage that is generated as an output of the wordline voltage booster circuit. A trimming circuit is electrically connected to the adjustable clamp circuit and is used to adjust the voltage level that the adjustable clamp circuit takes effect, if necessary.
The amount of voltage that is added or taken away from the voltage level that the adjustable clamp circuit takes effect at varies because of process variations experienced by the adjustable clamp circuit during fabrication. The voltage level varies because of variations in transistor sizes that are fabricated on the silicon substrate. The adjustable clamp circuit is comprised of transistors and, as such, the voltage level that the adjustable clamp circuit takes effect at is dependent on the threshold voltage (Vt) of the transistors used in the clamping path. As set forth above, since the voltage level of the boosted wordline voltage that is applied to the wordlines during read operations from the wordline voltage booster circuit is dependent on the voltage level that the adjustable clamp circuit takes effect at, the boosted wordline voltage can be adjusted to the preferred value of approximately 5.0 V by changing the voltage level at which the adjustable clamp circuit takes effect.
The preferred embodiment of the present invention allows the flash memory to maintain tight control of the boosted wordline voltage that is used during read operations, thereby increasing the reliability and durability of the flash memory. In the preferred embodiment of the present invention, the trimming circuit is electrically connected with a trimming decoder. The trimming decoder is used by the flash memory to adjust the voltage level at which the adjustable clamp circuit takes effect and, in turn, determines whether the wordlines will be exposed to a higher or lower boosted wordline voltage during operation. A plurality of content addressable memory (xe2x80x9cCAMxe2x80x9d) circuits is electrically connected to the trimming decoder. The CAM circuits are used to control the trimming decoder, which, as set forth above, indirectly controls the voltage level at which the adjustable clamp circuit takes effect with the trimming circuit.
The output of the wordline voltage booster circuit is electrically connected to a pass gate and at least one wordline decoder. As known in the art, a typical flash memory device contains several wordline decoders that are used to transfer various operational voltage levels to selected wordlines during an operation such as read, write and erase. The pass gate is electrically connected with an enable logic circuit, which controls the pass gate by enabling and disabling the pass gate during operation. In the preferred embodiment, the pass gate is also electrically connected with a supply voltage connection (Vcc). The enable logic circuit enables the pass gate before boosting the wordlines to initiate or pre-charge the wordlines using the voltage on the supply voltage connection (Vcc) prior to boosting the wordlines to the boosted wordline voltage.
As previously set forth, the voltage level at which the adjustable clamp circuit takes effect controls the voltage level of the boosted wordline voltage that is generated by the wordline voltage booster circuit. Due to process variations experienced during fabrication, the adjustable clamp circuit may take effect at a higher or lower voltage level than the preferred value of approximately 5.0 V. As such, the voltage level at which the adjustable clamp circuit takes effect may need to be adjusted up or down, depending on the characteristics of each flash memory chip. The determination of whether the predetermined voltage level, at which the adjustable clamp circuit takes effect, needs to be adjusted is made during testing. If an adjustment is required, the CAM circuits are programmed such that the trimming decoder causes the trimming circuit to add or subtract voltage to the voltage level that the adjustable clamp circuit takes effect.
Another preferred embodiment of the present invention discloses a clamp and trimming system for controlling a boosted wordline voltage generated by a wordline voltage booster circuit in a flash memory. The clamp and trimming system includes an adjustable clamp circuit that is electrically connected with the output of a voltage booster in the wordline voltage booster circuit. The voltage booster generates a predetermined gate voltage, which is clamped by the adjustable clamp circuit at a predetermined voltage level during operation. The predetermined voltage level at which the adjustable clamp circuit takes effect controls the voltage level of the boosted wordline voltage.
A trimming circuit is electrically connected with the adjustable clamp circuit for adjusting the voltage level at which the adjustable clamp circuit takes effect, thereby controlling the voltage level of the boosted wordline voltage that is generated by the wordline voltage booster circuit. The clamp and trimming system is capable of holding and adjusting the gate voltage generated within the wordline voltage booster circuit by the voltage booster to a predetermined voltage level, which corresponds to the optimal boosted wordline voltage that needs to be applied to the wordlines during read operations in the flash memory.
As set forth above, the present invention discloses a method of controlling a boosted wordline voltage that is used during a read operation in a flash memory. In the preferred embodiment, a gate voltage is generated with a voltage booster in a wordline voltage booster circuit. The gate voltage is clamped at a predetermined voltage level with an adjustable clamp circuit that is electrically connected to the wordline voltage booster circuit. If necessary, the predetermined voltage level may be adjusted with a trimming circuit that is electrically connected to the adjustable clamp circuit. The boosted wordline voltage is then generated with the wordline voltage booster circuit based on the predetermined voltage level that the adjustable clamp circuit clamps the gate voltage of the voltage booster.
The above-referenced methods and system disclose ways of providing tight control of the boosted wordline voltage that is applied to wordlines during read operations in a flash memory. Without these methods and systems, the boosted wordline voltage could be to high or low, thereby causing problems with data retention and the overall operation of the flash memory. If the boosted wordline voltage is too low, the states of the core cells in the wordlines cannot be read properly and the flash memory will fail. If the boosted wordline voltage that is applied to the wordlines is too high, the flash memory will experience gate disturb and data retention is reduced, causing reliability problems.
These and other features and advantages of the invention will become apparent upon consideration of the following detailed description of the presently preferred embodiments of the invention, viewed in conjunction with the appended drawings.